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djmoc
modified 10 years ago

4 bits Successive approximation adc

4
6
151
01:58:51
take 2 clock per bits + 3 clock to complete a conversion to start the circuit you need to toggle 1 time the logic button on the left.
published 10 years ago
hurz
10 years ago
I think this can be done a bit easier.
djmoc
10 years ago
surely but I didn't yet found how. I know uC do it 1 clock per bit + 1 clock but I don't know how.
hurz
10 years ago
Maybe you like this version http://everycircuit.com/circuit/4798576620208128
djmoc
10 years ago
I saw it before tryin to build mine but the problem is that it have to count every value. so for an 8 bits ADC you need 256 clock to pass from 0 to max, mine would take only 19 clock to do the same. as a final goal I don't really care about the logic complexity because I will implement it in an FPGA with a parallel output port, so I just need to be fast.
hurz
10 years ago
Good point!
djmoc
10 years ago
I made a faster version of this converter, the new one can run up to 4 time faster.

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