When the top input (input A) is at logic high, the corresponding transistor’s emitter base junction is reverse biased and the base collector junction is forward biased.
Transistor Q3 (base connected to a 1.6K resistor) gets base current from supply voltage Vcc and goes to saturation.
As a result of low collector voltage from Q3, transistor Q5 (collector connected to the 130Ω resistor) goes to cut off and on the other hand if another input is low, Q4 (emitter connected to the 1K resistor) is cut off and correspondingly Q5 is cut off and output is connected directly to ground through transistor Q3.
In a similar way, when both inputs are logic low, the output will be at logic high.
Enjoy...😎
