ALU with IO registers_2

258

03:06:36

With three 4 bit data lanes, a 2 bit opcode, and clock input. Warning: it really, REALLY lags. This is just a prototype for a much larger scale that I'm working on using software that doesn't limit the workspace; on a transistor level. Just thought I'd share the intermediate results.

published 8 years ago

Thrashard96

8 years ago

...technically it's just a logic unit, but it's possible to easily replace a logic gate at the input to a full adder.

zorgrian

8 years ago

What is the best way to remove the atrocities such as Mr big penis or others who are deliberately frying our minds with pro iCircuit propaganda and obscene language, ideas, racist crao etc?

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