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NAND SR Latch

@FalchionGPX
10 years ago
https://everycircuit.com/circuit/6144224272580608
Bottom output is Q Top output is Q' S R | Q Q' ________ (Description) 0 0 | 1 1 Both are ONES...both ON 0 1 | 0 1 RESET signal... OFF 1 0 | 1 0 SET .... signal... ON 1 1 | Q Q' Do Nothing! Behavior is inverse of the NOR SR latch. if both SET and RESET are 0, both top and bottom are ON. If both SET and RESET are on, no state-change occurs. If SET blips to 0, top is on. If RESET blips to 0, bottom is on. 1 1 (no change) (both on) 00 01 (top on) 10 (bottom on)
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