modified 8 years ago

CMOS tristate buffers - assistance wanted

00:37:41

I've been scratching my head about this one for the entire week - what are the correct methods of designing tristates, what benefits and what drawbacks does each design have? I've seen online the designs with one nMOS (or pMOS) used as a drain to source buffer controlled by the OE switch connected to the gate; CMOS designs in a previous fashion (similar to how the multiplexer input is handled); and an inverter design; all three are shown in this project.

Are there more ways to design this buffer?

published 8 years ago

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