A clock divide by 5 circuit using 3 x D flip flops and 8 logic gates. The lower flip flop (A - LSB) has the input of (not A, not C). The middle flip flop (B) has the inputs or ((A, not B, not C) or (not A, B, not C). The top flip flop (C - MSB) has the input (A, B, not C). The output is the right LED flashing at 1/5 the speed of the left LED which is directly output by the clock.
