Logic checker

A line shouldn't be driven by more than one gate. I'm not sure if I get your circuit, but maybe try merging all of your gates output into successive OR gates, until you have only one gate driving the line.

Only function drive circuit gates or logic

components in grey color are taken out of simulation and nit present for the simulator. Thats the first fault you do amd can be fixed with pullup or pulldown resistors. Second is what @Crypto_ says and can not easily sovled with a bunch of OR gates cuz one gate might block all other gates with a single set output to HIGH, so abconnected counternas result is probably not a good idea. Third is the relay startup workaround is for this circuit not needed cuz it does not have the CFS problem, while a 5V relay better not driven with 8V. Place a voltage source or modify your VCCS to 50mA/V. There is probably more to come, lets see

@890pp if I understand you right, you're trying see the logic of each gates? If so, this circuit might be better for your needs : http://everycircuit.com/circuit/6178771112296448