https://www.desmos.com/calculator/mxqcfom71t
(best viewed in desktop or desmos app)
On the left, the base is driven directly by a source with an offset to bias quiescent voltage between collector and ground (which is about (Vcc+Vb)/2). When biasing, it is better to design in terms of Thevenin voltage and resistance, when the desired voltage and resistance is achieved you can convert the circuit to a divider biasing (on the right).
To get the equivalent resitance for the divider network you need to solve 2 equations:
Eq.1: Rth=ab/(a+b)
Eq.2: Vcc/Vth=(a+b)/b
Where:
* Rth - Thevenin Resistance (resistance along Ib in the left circuit)
* Vcc - Source voltage
* Vth - Input quiescent voltage (voltage offset to achieve the desired biasing).
* a - Resistance between Vcc and base.
* b - Resistance between base and ground.
You can then rescale a and b so lower it's current (at least 10 times the base current).
The output waveform in the divider circuit is slightly different from the desired because of the filtering effect of the coupling capacitor, this also have to be taken with care since it affects the response of the circuit.
