modified 11 years ago

NAND latch and gated pulses

00:48:02

Two NAND gates set up as an RS latch. The latch output (Q) is set by taking the upper input (S) low. Further changes to S will not change the output. With S high, taking the lower input (R) low will reset the latch (Q will go low and Qbar high - this blocks the logic pulses until S is again taken low.

published 11 years ago

lenzrulz

11 years ago

Nice.

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