modified 8 years ago

Inverting CMOS three state buffer

00:39:59

Am I doing this right? I can't seem to figure out how it should look in the CMOS TL view. The high Z output here, even though it does fulfill the logic thresholds, should have stayed at exactly 0 or 5 volts.

published 8 years ago

jason9

8 years ago

Look good to me. It only still changes even when it’s in its “off” mode because of the parasitic capacitance delivering some of the voltage to the output as long as the output is left floating.

Thrashard96

8 years ago

Hmmm, thanks. I've been thinking about what's the correct design for it for a few days now

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