TTL clock generator

118

01:32:23

Any idea why this won't work?

published 10 years ago

stinus

10 years ago

Stijn

darrhunt

10 years ago

First, ground has to be connected.

ferlop

10 years ago

No, the ground doesn't need to be connected! :)

rich11292000

10 years ago

I thought logic gates are cmos and not ttl??? This is because they are a voltage controlled source and not current controlled source???

ferlop

10 years ago

rich you right, I forgot that little detail. But shuldn't cmos still work with this circuit, I mean oscillate?

GingerKing

10 years ago

Assume the top output is High and the bottom is Low. The top gate would see '1', '0' and would continue outputing a '1'. The bottom would see '0', '1' in the beginning and would switch to a '1'. Both gates outputing '1' cause all inputs to become '1'. Once the inputs become '1' gates output '0'. Repeat. The problem is that the analog inputs are messing up the 0v and 5v outputs. This makes them between 0 and 5v and EC freak out.

GingerKing

10 years ago

Oh actually.. im pretty sure this circuit requires gate delay which EC doesnt account for. Caps will do nothing if the gates are ouputing equal values because the caps will instantly charge and then the gates will instantly switch. This causes a terrible instantaneous feedback

ferlop

10 years ago

OK, thank you that makes sense.

ferlop

10 years ago

The solution was so simple, ARRRRGGGH@#$!*&!

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