Quite a neat little circuit, found online. Im thinking the way that it works is by biasing the first NPN into the capacitor, it is then pushing the emitter voltage of the transistor up to increase its collector voltage turning on the second NPN, which boosts the cap, once the cap has discharged enough the voltage rises at the emitter of the first NPN to start the cycle again.
Vcc = 3.3V for CMOS TTL
