Analog to digital conversion using half flash configuration. Three op amps act as voltage comparators and reference the voltage at 1/4 intervals. The comparators go logic high when the input is higher than their threshold, and the output is fed through logic gates to convert it to 2 bit binary. These bits are the most significant bits The output is then converted back to analog with 1/4 bit resolution. This output can then be compared to the input to extract the finer differences between the true signal and the convertet signal. This difference is then fed into three more comparators that further subdivide the resolution by another 1/4. These comparators are then fed into logic, converted to 2 bits which are then used as the least significant bits. The advantage to this over regular flash converters is that fewer comparators are needed for more precise bit resolution. For example, 4 bit full flash would require 15 comparators, whereas this half flash design only requires 6 comparators. A 24 bit full flash converter would require 8 million comparators, where a half flash would only require 36 comparators
