True RMS-to-DC Converter

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01:16:26

Using implicit rms computation via analog log/antilog circuitry. Due to implicit rms computation, there is a slight constant (DC) error as well as a ripple (AC) error. The ripple is minimized using a post KRC type LPF, but limits the input frequency to around 2KHz. Errors can further be minimized by increasing the capacitance (of capacitor located in feedback of OA following the BJTs), but at the cost of an increased response time. This cap should also be an electrolytic cap (when is EC giving us more components and design space??). 

Reference:
Based off "true rms converter" from ”Design with Operational Amplifiers and Analog Integrated Circuits", Sergio Franco, Chapter 13

published 7 years ago

hurz

7 years ago

Tested with some more wave forms and even with 1V offset and 1Vpeak AC it gives after increase of LPF capacitors sqrt(3/2)=1.2247 comes close to this theoretical value. 1V DC cause 1.01V which is just 1% error 😉 nice circuit even its a standard from a book, you have to bring it here on everycircuit to work! Good job!

calvin21

7 years ago

Thanks for the feedback @hurz👍 Did you also have some weird lagging issues with the simulation of the response?

calvin21

7 years ago

Seems to only be a problem with higher simulation speeds though

hurz

7 years ago

Yes, every periode of input it stops for a few seconds

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