Using implicit rms computation via analog log/antilog circuitry. Due to implicit rms computation, there is a slight constant (DC) error as well as a ripple (AC) error. The ripple is minimized using a post KRC type LPF, but limits the input frequency to around 2KHz. Errors can further be minimized by increasing the capacitance (of capacitor located in feedback of OA following the BJTs), but at the cost of an increased response time. This cap should also be an electrolytic cap (when is EC giving us more components and design space??).
Reference:
Based off "true rms converter" from ”Design with Operational Amplifiers and Analog Integrated Circuits", Sergio Franco, Chapter 13
