Level Protected IO

Used to protect Input-Output to ATMega1284. Right switches are for pull-up and pull-down to the MCU power rails. Top left switch has max input values (-15V through *Pmax*). Note 50V (shown as zener) will destroys the FET and then the MCU. Second left switch is to the gate of a high voltage MOSFET which needs 10V on it to operate. Perhaps to take power from a long PV string. Third switch has LED (or SSR e.g. Crydom series 1 D2410 3V@4mA) supplied with current source from battery power that the MCU can pull down. Vgs of level protection FET can be seen. Forth switch is a short. The MCU is not protected from this when it activates the pin pull up. Right LEDs work like ESD protection diodes in MCU. *Pmax* is a power limit, e.g. 10V source to drain is the max power of .25W, at 25mA. used on the following board: http://epccs.org/indexes/Board/Irrigate7/

published 11 years ago