4-bit Deserializer -ATTEMPT-

Here, I attempt to create a 4-bit Deserializer. I am not an expert in digital electronics, and do not know standard SerDes architectures. As a hobby, I try to create circuits from scratch as some sort of puzzle. The deserializer converts a stream of digital data (Serial) to Parallel data pulses. This circuit converts 4 4 bits of serially transferred data at a time. The converted data is interpretted by the decoder and displayed to the user with the seven segment display. THEORY: Each bit from the serial digital data source (OpAmp output) is pushed through a 4-bit shift register "horizontally" first for every positive edge of the clock. When all four bits are stored, a clock counter triggers a gating circuitry (D-Flipflops) connected in parallel to the stored 4 bits, passing these bits to the output "vertically" or in parallel to a decoder. At the same time, the counter is reset to zero. The cycle then repeats for the rest of the data stream. PS: feel free to modify the period and delay of the three logic stream sources to create your own pseudorandom -or not- digital data source. Here is another version of the same circuit: https://everycircuit.com/circuit/4676002535702528

published 4 years ago