About the schematic I found:
I found this schematic on google images. It was different from most of the other schematics and unlike the others used only two input gates. Also, while it does have a carry in, it has no carry out. Instead of a carry out, there are two outputs that are labeled G’ out and P’ out, despite there being no G’ in or P’ in. I removed the logic for the G’ out and P’ out since it wasn’t needed, and also since there was no carry out, I added in the logic for that by following the pattern provided by the rest of the carries in the adder. By looking closely at the schematic, I can clearly see that the carry-out I made should work flawlessly unless I missed something vital. By the way, the carry out goes to the decimal point on the output display.
Link to the circuit schematic:
https://ai2-s2-public.s3.amazonaws.com/figures/2017-08-08/f2e00bed8b4a1b6700b83459a9c27ef1ccd37d87/2-Figure1-1.png
About the circuit:
On the left are some logic sources, divided into three groups. The top group has just one logic source, and the other two have four sources each. The lone source is the carry in, and each group is a 4 bit binary input (least significant bit on top). The longest path in this circuit is between the least significant bit of either of the inputs and the most significant bit of the output, and covers six gates. For comparison, the longest path in the corresponding ripple-carry adder which is between carry-in and carry-out would cover 8 gates (assuming its wired to minimize the number of gates between carry-in and carry-out on each full-adder by choosing which input of each full-adder is the carry-in, otherwise it could be as many as 12 gates total in worst case scenario). The logic here could be improved to reduce the longest signal path from six gates, but it would require logic gates with more than two inputs.
