modified 9 years ago

D flip flop- internal structure

01:06:30

In D flip flop, the output is same as input but after a small delay when clock is present.
Upper logic source is clock and lower is input
The inputs are clock and input data and the outputs are A and A'.
Operation:
When clock is applied,
 if input is 1 then A=1 and A'=0.
If input is 0 then A=0 and A'=1
When clock is absent,
O/p is previous state.
Fun fact-
If the number of inverters are even then it is a D flip flop.
If the number of inverters are odd then it is a T flip flop.
You can check the T flip flop which I made.

published 9 years ago

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