This ADC uses the successive approximation DAC design. This design is more complex than a standard ramp counter ADC, but it's really faster.
You can get more infos here (well explained) : http://www.hardwaresecrets.com/how-analog-to-digital-converter-adc-works/
This second version uses 2 SR latches (thanks to @EvilDuck95) : one to block the first (fast approx.) counter and another to stop the precision counter.
The voltage source on the left is Vref,
The right one is the input you want to compare.
The button on the bottom right corner is the counter and memories reset.
The output is in Hexa, and has to be read from bottom to top (LSB is the top resistor, MSB is the lowest resistor).
If you find bugs ... let me know :)
