Not sure if the N FET is configured "realistically".
Trying to approximate an FQP30N06L.
I increased the "channel width" and that seems to get the FET "fully open" (or at least much more open than the default N FET) at approximately 5V Vgs, so it seems to be closer to a "logic level" N FET now.
But since I have no idea how the FET settings are supposed to be used I may have created a FET that is purely imaginary/theoretical instead. :-/
The BJT at the bottom dumps the current/charge from the FET gate if the current through the bottom resistor gets too high, creating a negative feedback "loop".
