JK flip-flop

179

01:29:45

CLK signal in the middle. J input on the top, K input on the bottom.

The output only flips on the rising edge of the clock signal.

If J=0, K=0, the output persists.
If J=1, K=0, the output sets to 1.
If J=0, K=1, the output sets to 0.
If J=1, K=1, the output toggles.

published 2 years ago

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