2 Wire Data Packet Transfer - TX-RX - MK-5 - With Capacitive Memory

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04:48:41

Data transfer via 2 wires.
Originally used counters to latch the bits on the RX side. Now using capacitive memory. (trying to save space, but didn't gain much).
Does not work well at high sim speeds.
LH side is TX & RH side is RX.
Set the bits for the TX to display a number. That number will then be displayed on the RX side.
The sequencers on each side are synchronised via a shared clock pulse wire. The TX sequencer reads the bits set for the TX display (4 clock pulses), and sequentially transmits them to the RX. The RX sequencer then reads the bits and sends them to the 4 latches (top right). This creates a latched bit set.  A fifth pulse then loads this bit set into the counter that feeds the RX display.

published 10 years ago

jenrico

10 years ago

Awesome nice work

Secuture

10 years ago

Did you guys hear about some thing about parallel single wire digital transmision using multi frequency analog carrier wave ? In simple words it is encoding digital signal into few different high frequency careier sine waves. They can exist together in one place not interfering each other and decoded by frequency discriminators at the same time. U know something as in cable tv where u have many digital streams every for particular channel but u decode only single one. Here u can use all to build single image. Its quite interesting idea isn't it?

Karma247

10 years ago

Sounds interesting. I have done a single wire version, but couldn't fit it on one page. It is separate TX & RX at the moment. It's a bit of a botch though, using different amplitude pulses. Need more space on here.

Karma247

10 years ago

Thanks jenrico.

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