VDC-VDC Step Down Regulator

Switching regulator that 'chops' the input voltage (Vin) down to a voltage determined by the resistor divider that is feeding back to the opamp. Once the feedback voltage (Vfb) raises above the reference voltage (Vref) the opamp turns on at max voltage (5V), the opamp output voltage is put across the gate of a JFET setup to function as an inverter. This inverted opamp signal that was previously at 5v and now at 0v turns off the JFET at the input. This brings Vfb back down below Vref and turns the opamp off, causing the JFET at the input to turn back on. This causes the output to oscillate around a voltage that satisfies the voltage divider equation of 0.6V=Vout*(Rb / (Rb + Rt)). Advantages: Vout is independent of Vin provided that Vin>Vout. Disadvantages: Multiple reference voltages required (5v and 0.6v in this example) A rippled output (not seen in this simulation but the true Vout would ripple. (Note: to restart, turn the switch in the middle to the 1 volt side and start the simulation, then flip the switch to the normal position. This is due to EC not being able to solve the circuit from the start.)

published 9 years ago