Analog to Digital Single Bit Half Flash

328

02:52:11

This ADC uses the half flash pipeline configuration, but each stage only handles a single bit division. This allows for the logic stage to be removed and instead the output is the pure resultant of the comparators, op amp adders and subtractors. I believe this design could be used for more efficient pipeline converters with high bit resolution. Normal pipeline conversion typically sacrifices circuit size for response time, but this design truly provides both speed and scalability.

published 2 years ago

592azy2circuitdude

2 years ago

Again, this is a great example. In your last ADC post, I mixed up my terms. The circuit is a Pipeline ADC, which is basically a daisy chain of parallel, aka flash ADCs. I hope I didn't confuse you.

592azy2circuitdude

2 years ago

Your observations about speed are correct. The only hitch is when scaling to high bit resolution, the errors due to component variations build up. But now, with high accuracy analog amplifiers and error correction techniques, larger resolution is becoming possible. Digikey has a great article you'll probably find interesting titled "Analog Basics - Part 3: Pipeline ADCs and How to Use Them."

joshinator

2 years ago

I double checked the terms, I should say this is a pipeline, thanks! And I was just gonna say, I can see how error could build at each stage but like you said there must be ways to handle error correction. I'll check out the article! 😁

joshinator

2 years ago

I should mention I'm just a student on my second year for a transfer degree to an EE school. So I'm still learning an awful lot. I appreciate the resource you sent!

592azy2circuitdude

2 years ago

Yeah, I'm still learning a lot about electronics, too (mostly analog stuff now). Keep it up 👍.

benjaminerickson86

2 years ago

hm i lik the displa

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