if we do a nodal analysis on the non-inverting node we will find that voltage at that point will be (4V1+2V2+1V3)/(4+2+1).
It is basically a non-inverting summer, so if V1= V2 = V3 = logic level. Then output will be V(4B2+2B1+B0)/7 where B0 is the LSB, B2 is the MSB and V is Logic High level Voltage.
Similarly we can construct higher width DACs also. Accordingly I have set the gain to cancel the denominator. However it is upto us to choose the scaling factor(gain).
The resistor need not to be of these exact same value but should be of this exact same ratio.
But this will not work exactly as the inverting, where even if we leave a pin floating it used to work. Here we have to make sure that all pins are 0 or 1(logic high). IF YOU leave a pin floating then the loop won't be completed properly and node voltage won't be as expected.
