@Muse - This circuit models a 4-channel (4-cell) 1-bit dynamic RAM array sharing a common bitline (#bl). Each storage channel is a classic 1T1C (one transistor, one capacitor) DRAM memory cell.
### Operating Instructions
1. **Refresh Array**:
* Turn #DATA off to avoid charging the storage capacitors
* Turn #REFR on to stop current racing in capacitors
* Turn #WR on to provide access to channels then off again
* Turn #REFR off before continuing
* Can also be used to write to all channels at once
2. **Select Channel**:
* #S0 and #S1 are select bits
* Translates from binary to decimal to select channel 0-3 (eg. #S0 high and #S1 low gives the binary number 01, which would select #C1)
3. **Write Operation**:
* Set the data state on #DATA ($0$ for low, $1$ for high).
* Activate the desired channel by turning its wordline on (e.g., #S0 low and #S1 high for #w2).
* Press the write button #WR to let current flow down the bitline #bl
* The capacitor (e.g., #C0) charges or discharges to store the bit.
* Turn the wordline off to preserve the bit state inside the capacitor.
