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nimaid
modified 1 year ago

NMOS D Flip-Flop with Preset and Clear

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00:54:35
An edge-triggered D Flip-Flop in NMOS. 3 SR latches. A single additional transistor is used as a combo input to 3 nand gates in order to clear each SR latch on a low signal. Similarly, another transistor is used to preset the latches on a low signal.
published 1 year ago

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