Top circuit: Full single bit adder with carry in and out at the. Button circuit: Full single bit subtractor with borrow in and out at the bottom. Right circuit: 2-to-1 multiplexer with selector control signal at the bottom. Uses a clocked D-latch in the output to prevent glitches when selecting between inputs that are both in the TRUE state. Alternatively, tri-state buffers connected to control signals could be added to each AND gate to open contradicting gates with high impedance. The control signals would need to be precisely clocked and mutually exclusive.
