Here, I attempt to create a Serializer.
It converts parallel data to serial data.
Theory:
Each bit in the 4-bit parallel data is fed to one input leg of 4 AND gates respectively.
In order for the input to be copied to the output, an Enable signal must be present on the other leg.
This Enable signal is provided by the counter circuit + the combinational logic gate circuitry.
1 AND gate is activated for each count of the counter from 1 through 4.
When the count reaches 5, a signal is triggerred to reset the count to 1, thus repeating the pattern.
The frequency for the counter should be the 3rd harmonic of the frequency of the parallel input refresh rate.
