Motorola ECL 10,000 OR/NOR gate, transcribed from https://upload.wikimedia.org/wikipedia/commons/b/b2/ECL.svg . Logic levels and other info from http://www.onsemi.com/pub/Collateral/TND309-D.PDF .
The output transistors are on the right. The upper one is non-inverted (OR), the lower one inverted (NOR). Pull-down resistors have been added to simulate the inputs of the following gates.
Logic levels:
0: -1.75V
1: -0.9V
Hmm! Those output curves make it look like it would struggle with 5MHz, but I remember an ECL counter capable of 600MHz. Maybe it's an artefact of the pull-down resistors. I want to see it drive another gate; will do that eventually. Maybe the diagrams on page 4 of TND309-D are relevant.
MECL 10K gates are supposed to be capable of differential output, even driving long twisted-pair cables, but here the outputs are mis-matched: the non-inverting output is positively flakey! The diagram I followed only has resistor values. I wonder what other component parameters need to be adjusted to make it right?
