2 Wire Data Packet Transfer - TX - RX - MK-2

Data transfer via 2 wires LH side is TX & RH side is RX. Set the bits for the TX to display a number. That number will then be displayed on the RX side. The sequencers on each side are synchronised via a shared clock pulse wire. The TX sequencer reads the bits set for the TX display (4 clock pulses), and sequentially transmits them to the RX. The RX sequencer then reads the bits and sends them to the 4 latches (top right) (had to use counters to create the latches). This creates a latched bit set. A fifth pulse then loads this bit set into the counter that feeds the RX display. I initially used a 555 for the clock pulse, but had to ditch this due to space constraints. Then used a pulse generator, which caused everything to run very slowly, so there was a several second delay between setting the TX number and seeing it on the RX. Also, sometimes the wrong number is displayed if the the bits are set part way through the sequencer cycle. This will then correct is self next time the sequencer cycles. As recommended by roops1967, I replaced the pulse gen with a self clocking counter. This made a huge difference. A big thanks to roops1967 For the help with speeding things up.

published 10 years ago