This circuit consists of just a pair of resistors and a voltage source but allows to emulate J-FET having MOSFET as a basic model. The adjustment of MOSFET model parameters is also needed (first of all you need to reduce `Lambda` parameter several times, also tweak `VTO` and `KP` to get desired characteristics). The value of voltage source affects to cut-off voltage of emulated J-FET : J-FET transistors despite of MOSFETs have some initial drain current even if the voltage applied to gate terminal (relative to the source) is zero hence some minimal inverse voltage (potential of of gate is lower the potential of source (for n-channel J-FET)) is needed to be applied to reduce drain current to zero. This is typical operating mode for J-FET when operating point lies somewhere in between cut-off and "initial state" (coressponging to V_GS = 0) The lack of this simulation is a quite low operating frequency of the device caused by enormous values of the input capacitance of MOSFET's in compare with J-FETs (hundreds of pF vs 2-10 pF). Here you can see the family of static characteristics namely dependence I_drain of V_drain-source for each V_gate-source changing from 0V to -3V with increments of 0.3V
