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1bit ALU
The 1-bit ALU (Arithmetic Logic Unit) is the fundamental building block of the complete 4-bit ALU. It processes one bit of data at a time and forms a single "slice" that, when replicated four times and chained together, produces the full 4-bit ALU.
1. Inputs.
The 1-bit ALU accepts two single-bit data inputs — A0 and B0 — representing one bit position of the operands. It also accepts four select lines (S3, S2, S1, S0) which together form a 4-bit operation code determining which of the 16 available operations is performed. Additionally, a Carry-In (CI) signal is accepted for arithmetic operations that require it.
2. Internal Structure
The 1-bit ALU is composed of three functional units:
Arithmetic Unit contains three separate adder circuits. The first is the main adder-subtractor, which handles both addition and subtraction. It uses the XOR trick on the B input — when the Sub control signal is active (derived automatically from the select lines when operation 1001 is selected), each B bit is inverted and CI is forced to 1, converting the adder into a subtractor using 2's complement. The second and third are dedicated INC/DEC adders for A and B respectively. These use a single NOT gate connected to CI, feeding NOT(CI) into all internal B inputs. When CI=1, the adder increments its input by 1; when CI=0, it decrements by 1, all without requiring a separate circuit for each function.
Logic Unit contains eight individual logic gates — AND, OR, NOT A, NOT B, XOR, XNOR, NAND, and NOR — all sharing the same A0 and B0 inputs and operating simultaneously in parallel. XNOR is derived by adding a NOT gate after XOR, NAND by adding a NOT gate after AND, and NOR by adding a NOT gate after OR.
Shift Unit implements two circular shift operations using pure wire routing with no logic gates. For Circular Shift Right A, the LSB of 4bit number (A0 in context of the full ALU) wraps around and connects as the input to the bit 3 position making it the MSB ,For Circular Shift Left B MSB (B3) wraps to LSB.
Since these are circular shifts, no bits are lost and no carry is generated.
3. Operation Selection (16:1 MUX)
All functional units operate simultaneously and produce their results continuously. The 16:1 Multiplexer acts as the selector — it takes all 16 operation outputs as inputs and, based on the 4-bit select code (S3 S2 S1 S0), passes exactly one result to the output. The Sub control signal for the adder-subtractor is also derived automatically from the select lines using a simple AND gate combination, so no manual intervention is needed when switching between addition and subtraction.
4. Output
The 1-bit ALU produces a single 1-bit result from the selected operation, plus a Carry-Out signal from arithmetic operations which connects to the Carry-In of the next slice in the 4-bit chain.
5. Operation Selection Code(S3 S2 S1 S0)
0000-0111 Logic Unit
0000 AND
0001 OR
0010 NOT A
0011 NOT B
0100 XOR
0101 XNOR
0110 NAND
0111 NOR
1000-1101 Arithmetic Unit
1000 ADD
1001 SUBTRACT
1010 INCREMENT A
1011 DECREMENT A
1100 INCREMENT B
1101 DECREMENT B
1110-1111 Shift Unit
1110 Circular Shift Right A
1111 Circular Shift Left B
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