This works very similarly to my first clock doubler, but with a small capacitor instead of a comparatively large inductor. Op-amp voltage limits are +/-12V instead of +/-24V, and the current it supplies peaks at at 500μA instead of 4mA. In both designs the peaks (+5V and 0V) are held while the op-amp's output is changing, but when it reaches its limit the voltage collapses to the 2.5V reference value. The 2 comparators and the or gate rectify the signal as if it were AC while cleaning it up.
I haven't spent so much time tweaking this one as the other one. It's got the same 'ripple' between 1.97 and 2.03MHz.
