modified 9 years ago

Logic levels using LDR

00:40:57

The potentiometer simulates a 2Mohm LDR, when is dark, resistance increase and the voltage in base turns on the transistor, the 100k resistor creates a voltage divider but this voltage is not certainly in the acceptable logic levels so I used a comparator with another voltage divider as VREF. In this way we make sure we have an acceptable logic level for CMOS and TTL inputs. If u have a idea to make better this design, tell me, thanks for watch (:

published 9 years ago

whedcgfjqkf

9 years ago

Downlo

whedcgfjqkf

9 years ago

Downloathe

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