circuit on the left has the NMOS sourcing current to the inductive load, high side driving. the circuit on the right has the NMOS sinking current from the load, low side driving.
N channel devices can be switched on in two ways:
1. the gate terminal voltage goes Volts Turn On (Vto) Volts above the source terminal voltage.
2. the source terminal goes Vto volts below the gate voltage.
notice in the left side circuit that switching the gate on does not turn the mosfet completely on - the little blue indicator is not vertical. the fet is now operating in its pinch region and has a high resistance, so the resistance between the drain and source terminals (Rds) is quite high. the voltage drop across the drain and source terminals behaves the same as a regular resistor; power is wasted to create heat. to fully saturate the fet and get the Rds to the lowest possible value, the gate voltage also has to also go Vto Volts above the drain terminal as well. Lower resistance means lower voltage drop and thus less power wasted.
the next problem in the left hand circuit is the coil itself. when current through a coil of substantial inductance is switched off, the emf pulls the voltage low. If the voltage on the gate is 0V, and the coil pulls the voltage on the source terminal Vto Volts below the gate pin, the fet will switch back on - we've lost control of the fet. The right circuit does not have this problem as the source is plugged directly to ground; it can't go below 0. the voltage on the drain terminal can vary up or down, but it won't turn the fet on.
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